1. Field of the Invention
This invention relates to a DMA (Direct Memory Access) circuit and computer system which directly access and transfer memory data, and in particular relates to a DMA circuit and computer system which perform DMA transfer over many channels.
2. Description of the Related Art
In order to improve the speed of data processing in computer systems, DMA (Direct Memory Access) transfer is utilized for data transfer between CPUs. In DMA transfer, a DMA circuit receiving an instruction from a CPU directly accesses memory, reads data, and transfers the data to another CPU. In recent years, with the growing complexity of computer systems, the need has arisen for DMA transfer between numerous CPUs.
In such a computer system, there is a need for a single CPU to simultaneously perform DMA transfer to a plurality of CPUs. In this case, by implementing numerous DMA channels in the DMA circuitry, DMA transfer control can be executed in parallel in response to a DMA transfer instruction by a CPU, so that the load on CPUs can be alleviated.
FIG. 11 shows the configuration of a conventional DMA circuit in which are implemented n DMA channels (where n is greater than one). As shown in FIG. 11, the DMA transmission module has an MPU 100, memory 110, and DMA transmission circuit 120. The DMA transmission circuit 120 has a data reception arbiter 130 to receive data from the memory 110, a data buffer 140 to buffer data for transfer, a data transmission arbiter 150 for sending data to a switch module 200, and n DMA transmission channel circuits 160-1 to 160-n.
The MPU 100 writes transmission data to the memory 110, and then issues a transmission instruction to an arbitrary DMA transmission channel (for example, 160-1). The DMA transmission channel 160-1 issues a data receive request (REQ) to the data reception arbiter 130, and acquires the data from memory 110. The data from memory 110 is stored in the data buffer 140.
Next, upon receiving notification of completion (storage in the buffer 140 completed) from the data reception arbiter 130, the DMA transmission channel 160-1 issues a transmission request (REQ) to the data transmission arbiter 150. By this means, transmission data in the data buffer 140 is sent to the data bus (here, a switch module 200) from the data transmission arbiter 150. The DMA transmission channel 160-1 waits for a completion (CMP) response from the data transmission arbiter 150, and upon completion of data transmission, issues a completion notification to the MPU 100 (see for example Japanese Patent Laid-open No. 7-028477).
In order for the MPU 100 to start this series of actions on a plurality of channels, it has been necessary to implement n data transmission channels, 160-1 to 160-n, within the DMA transmission circuitry (LSI) 120.
Thus by providing a plurality of DMA channels in the DMA circuitry, the CPU (MPU) can start a plurality of DMA channels to perform a plurality of DMA transfers, and can execute parallel DMA control.
However, in conventional DMA circuitry it is necessary to implement a plurality of DMA transmission channel circuits, resulting in an increase in the number of gates (circuit scale) of the LSI (DMA transmission circuit). For example, in the configuration example of FIG. 11, because the switch module 200 is provided with eight ports, it is necessary to implement a maximum of seven DMA channel circuits. Hence there is the problem that the package must be increased according to the number of gates, incurring increased LSI unit costs and development costs.